1. Field of the Invention
The present invention relates to a dynamic random access memory (referred to hereinafter as dynamic RAM) and particularly to a dynamic RAM capable of performing static operation in columns to fulfill a quick access function.
2. Description of the Prior Art
Most of dynamic RAMs of these days have a quick access function such as a fast page mode or a static column mode in which a cycle time can be decreased to suitably perform high-speed processing required in a memory for image processing or the like. In order to realize such a high-speed mode, a conventional dynamic RAM has columns comprising a static circuit as in a static RAM which does not need to be precharged. In such a conventional dynamic RAM, an input/output (referred to hereinafter as I/O) line for inputting and outputting data is constantly pulled up at a predetermined DC potential through an I/O load. However, if the I/O line is constantly pulled up at the DC potential, the potential on the I/O line can not immediately be lowered because of the existence of the I/O load when data "0" is to be written, and thus it takes time to write data. Therefore, a structure for preventing the above described disadvantage is adopted, in which the I/O load is rendered inactive during a writing cycle so as to be disconnected from a DC power supply (refer to Japanese Patent Laying-Open Gazette No. 60-179993 or IEEE J. Solid-State Circuits, vol. SC-20, pp. 894-902, Oct. 1985).
FIG. 1 is a circuit diagram showing a main part of a conventional dynamic RAM in which the above described structure is adopted. In FIG. 1, a dynamic RAM comprises a sense amplifier 1, a memory cell 2, a write buffer circuit 3, a row decoder 4a, a column decoder 4b, an I/O load 5, a pair of bit lines 6 and 7, a pair of I/O lines 8 and 9, MOS transistors 10 and 11 for switching between the pair of bit lines 6 and 7 and the pair of I/O lines 8 and 9, MOS transistors 12 and 13 constituting the I/O load 5, and a word line 15.
Operation in a writing cycle of the dynamic RAM of FIG. 1 will be described by taking the fast page mode as an example.
As shown in a timing chart of FIG. 2, writing operation is enabled when a row address strobe signal RAS, a column address strobe signal CAS and a write enable signal R/W applied from a CPU are all at a low level.
First, when the row address strobe signal RAS changes to the low level, a row address is selected by the row decoder 4a and a word line 15 corresponding thereto attains a high level. When data appears to a given extent from the memory cell 2 connected to the word line 15 as a potential difference between the bit lines 6 and 7, the sense amplifier 1 is activated whereby one of the potentials of the bit lines 6 and 7 is amplified to a source potential Vcc and the other is set to a ground potential GND. Subsequently, when the column address strobe signal CAS changes to the low level, the column decoder 4b is activated and a selected output Yi of the column decoder 4b attains the high level. As a result, gates of the MOS transistors 10 and 11 are opened, whereby the pair of bit lines 6 and 7 are connected with the pair of I/O lines 8 and 9. Thus, even in the writing cycle, the same operation as in a reading cycle is effected at an early stage of the writing cycle. In this state, data is written forcedly into the memory cell 2. Subsequently, the following operation is performed.
When the write enable signal R/W is turned to the low level, a read/write indicating signal W is turned to the low level in the dynamic RAM. The signal W is commonly applied to gates of the MOS transistors 12 and 13 of the I/O load 5 and to the write buffer circuit 3. Accordingly, when the output of the signal W is turned to the low level, the I/O load 5 is rendered inactive, whereby the pair of I/O lines 8 and 10 are disconnected from the DC source. At the same time, the write buffer circuit 3 is activated. When write data D.sub.in is supplied to the write buffer 3, the write buffer circuit 3 sets one of the I/O lines 8 and 9 to a high level approximate to the source potential Vcc and sets the other to a low level equal to the ground potential GND, dependent on "0" or "1" of the data D.sub.in. Those potential levels are transmitted to the pair of bit lines 6 and 7 through the pair of I/O lines 8 and 9. On that occasion, if the write data is different from the data already stored in the memory cell 2, that is, if data of "1" previously stored in the memory cell 2 is renewed and data of "0" is written therein for example, the potential level of the bit line 6 becomes slightly lower than that of the other bit line 7. As a result, the output level of the sense amplifier 1 is inverted, whereby the bit line 6 is set to the ground potential GND and the other bit line 7 is set to the source potential Vcc. Thus, writing of data into the memory cell 2 is completed.
In the dynamic RAM having the above described structure, one of the I/O lines 8 and 9 is set to the potential approximate to the source potential and the other is set to the ground potential in the data writing cycle, while in the data reading cycle, the output level of the sense amplifier 1 does not need to be inverted and the I/O lines 8 and 9 are set to almost the same potential. Accordingly, if one data writing cycle is completed for example, it is necessary to charge the I/O line of the low level to a predetermined potential (as indicated by V.sub.ct in FIG. 2) so that the dynamic RAM is prepared for the subsequent reading or writing cycle. However, the I/O lines 8 and 9 are connected with a number of pairs of bit lines 6 and 7 and the pair of I/O lines 8 and 9 have a large capacitance load accordingly the I/O line 8 or 9 cannot be instantly charged up to the predetermined potential by the capacity of the I/O load 5. Thus, a little time is required for the I/O line 8 or 9 to attain the predetermined voltage V.sub.ct.
In the fast page mode, a change of column addresses is permitted in a state in which the column address strobe signal CAS is at the high level, whereby a different column address can be selected. When the column address strobe signal CAS is at the high level, the read/write indicating signal W also attains the high level accordingly. As a result, the gates of the MOS transistors 12 and 13 of the I/O load 5 are opened and the I/O line 8 or 9 of the low level is charged. The charging takes a time t.sub.d because of the above described capacity of the I/O load 5.
A different column address is selected with the I/O line 8 or 9 being at a potential lower than V.sub.ct and if the potential on the bit line 6 or 7 corresponding to the newly selected column address is considerably different from the potential on the I/O line 8 or 9 (for example, if the I/O line 8 of the potential lower than V.sub.ct is coupled with the bit line 6 connected to the memory cell 2 in which "1" is stored), the pair of I/O lines 8 and 9 themselves function as a kind of a source because of the large capacitance load of the I/O lines 8 and 9. As a result, although the write data D.sub.in is not at all supplied to the write buffer 3, the output level of the sense amplifier 1 of the bit lines 6 and 7 is inverted. The inversion of the output level of the sense amplifier 1 causes erroneous writing of data in the memory cell 2. In the above described example, the data of "0" is erroneously written in the memory cell 2.
In order to prevent such errors, the column address cannot be changed during the period t.sub.d after the column address strobe signal CAS attains the high level until the potential of the I/O line 8 or 9 rises to the predetermined potential V.sub.ct and it is necessary to wait for a lapse of this period t.sub.d. Accordingly, a delay is caused in timing for permitting a change of the column address. In other words, there is caused a delay in access time of the column address.
In the static column mode, when the write enable signal R/W attains the high level, a change of the column address is permitted, but there is also caused a delay in access time of the column address for the same reason as described above.